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NB3N3011 3.3 V 100 MHz / 106.25 MHz PureEdge Clock Generator with LVPECL Differential Output
http://onsemi.com Description
The NB3N3011 is a Fibre Channel Clock Generator and uses a 26.5625 MHz crystal to synthesize 106.25 MHz or a 25 MHz crystal to synthesize 100 MHz. The NB3N3011 has excellent <1 ps phase jitter performance over the 637 kHz - 10 MHz integration range. The NB3N3011 is packaged in an 8-Pin 4.4 mm x 3.0 mm TSSOP, making it ideal for use in systems with limited board space.
Features
MARKING DIAGRAM
311 YWW AG
TSSOP-8 DT SUFFIX CASE 948S A Y WW G
* PureEdge Clock Family Provides Accuracy and Precision * One Differential LVPECL Output * Crystal Oscillator Interface Designed for Fundamental Mode 18 pF * Output Frequency: 106.25 MHz (26.5625 MHz Crystal) or 100 MHz * * *
(25 MHz Crystal) VCO Range: 760 MHz - 950 MHz RMS Phase Jitter @ 100 MHz, using a 25 MHz Crystal (637 kHz - 10 MHz): 0.29 ps (Typical) RMS Phase Noise at 106.25 MHz Phase noise: Offset Noise Power 100 Hz -108 dBc/Hz 1 kHz -122 dBc/Hz 10 kHz -135 dBc/Hz 100 kHz -135 dBc/Hz 3.3 V Power Supply -40C to 85C Ambient Operating Temperature These are Pb-Free Devices* Parallel Resonant Crystal (25 MHz or 26.5625 MHz)
= Assembly Location = Year = Work Week = Pb-Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet.
* * *
XIN 25 MHz or 26.5625 MHz X OUT
Crystal Oscillator
Phase Detector
Charge Pump
VCO 850 MHz w/26.5625 MHz Ref.
N =B8
LVPECL Output
Q
100 MHz or Q 106.25 MHz
M = B32
Figure 1. Logic Diagram
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
October, 2006 - Rev. 0
1
Publication Order Number: NB3N3011/D
NB3N3011
VCCA VEE XOUT XIN 1 2 8 7 VCC Q Q NC
NB3N3011
3 4 6 5
Figure 2. Pinout (Top View) Table 1. PIN DESCRIPTION
Pin 1 2 3 4 5 6 7 8 Symbol VCCA VEE XOUT XIN NC Q Q VCC Type Power Power Input Input Unused Output Output Power Description Positive Analog Power Supply Pin. Connected to VCC with filter components (See Figure 8). Negative Supply Pin. Crystal Input (OUT). Crystal Input (IN). No Connect. Inverted Differential Output. Typically terminated with 50 W to VCC-2.0 V. Noninverted Differential Output. Typically terminated with 50 W to VCC-2.0 V. Positive Digital Core Power Supply Pin. Connected to 3.3 V.
Table 2. ATTRIBUTES
Characteristic ESD Protection Moisture Sensitivity (Note 1) Human Body Model Machine Model Pb-Free Pkg, TSSOP-8 Value > 6 kV > 200 V Level 3 UL 94 V-0 @ 0.125 in 4150
Flammability Rating Oxygen Index: 28 to 34 Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol VCC VI IO qJA TSTG Supply Voltage Inputs Output Current Thermal Resistance (Junction-to-Ambient) Storage Temperature Continuous Surge 0 Lfpm 500 Lfpm Parameter Value 4.6 -0.5 to VCC + 0.5 50 100 142 103 -65 to 150 Unit V V mA C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
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NB3N3011
Table 4. POWER SUPPLY DC CHARACTERISTICS, (VCC = 3.3 V 5%, TA = -40C to 85C)
Symbol VCC VCCA ICCA IEE Parameter Core Supply Voltage Analog Supply Voltage Analog Supply Current Power Supply Current Included in IEE Conditions Min 3.135 3.135 Typ 3.3 3.3 19 27 Max 3.465 3.465 23 31 Unit V V mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.
Table 5. LVPECL DC CHARACTERISTICS, (VCC = 3.3 V 5%, TA = -40C to 85C)
Symbol VOH VOL VSWING Parameter Output High Voltage (Note 2) Output Low Voltage (Note 2) Peak-to-Peak Output Voltage Swing Conditions Min VCC - 1.4 VCC - 2.0 0.6 0.75 Typ Max VCC - 0.9 VCC - 1.7 1.0 Unit V V V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Outputs terminated with 50 W to VCC - 2.0 V. See Figures 4 and 12.
Table 6. PIN CHARACTERISTICS
Symbol CIN Parameter Input Capacitance Conditions Min Typ 4 Max Unit pF
Table 7. CRYSTAL CHARACTERISTICS (Fundamental Mode 18 pF Parallel Resonant Crystal)
Parameter Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Conditions Min 24 Typ Max 30 50 7.0 Unit MHz W pF
Table 8. AC CHARACTERISTICS, (VCC = 3.3 V 5%, TA = -40C to 85C (Note 4))
Symbol fOUT tjit() Parameter Output Frequency RMS Phase Jitter (Random) (Note 3) Conditions 24 MHz - 30 MHz Crystal (Typ. 25 MHz - 26.5625 MHz) 106.25 MHz; Integration Range: 637 kHz -10 MHz 100 MHz; Integration Range: 637 kHz -10 MHz tR/tF odc Output Rise/Fall Time Output Duty Cycle 20% to 80% (See Figure 7) (See Figure 6) 275 48 Min 96 Typ 100/106.25 0.29 0.29 600 52 ps % Max 120 Unit MHz ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. Please refer to the Phase Noise Plot. 4. Output terminated with 50 W to VCC- 2.0 V. See Figures 4 and 12.
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NB3N3011
NOISE POWER (dBc)
OFFSET FREQUENCY (Hz)
Figure 3. Typical Phase Noise at 106.25 MHz
PARAMETER MEASUREMENT INFORMATION
2V Phase Noise Plot VCC LVPECL Z = 50 W VEE Q 50 W -1.3 V " 0.165 V f1 Offset Frequency f2 Q SCOPE 50 W Noise Power Z = 50 W
Phase Noise Mask
RMS + Area Under the Masked Phase Noise Plot
Figure 4. Output Load AC Test Circuit (Split Power Supply)
Figure 5. RMS Phase Jitter
Q Q Pulse Width tPERIOD odc + tPW
Q Clock Outputs Q
80% 20% tR
80% VSWING 20% tF
tPERIOD
Figure 6. Output Duty Cycle/Pulse Width/Period
Figure 7. Output Rise/Fall Time
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NB3N3011
APPLICATION INFORMATION
Power Supply Filtering
The NB3N3011 is a mixed analog/digital product, and as such, it exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The NB3N3011 also generates sub-nanosecond output edge rates, and therefore, a good power supply bypassing scheme is a must. The NB3N3011 provides separate power supplies for the digital circuitry (VCC) and the internal PLL (VCCA). The simplest form of noise isolation is a power supply filter on the VCCA pin. Figure 8 illustrates a typical power supply filter scheme. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. The purpose of this design technique is to try and isolate the high switching noise of the digital outputs from the relatively sensitive internal analog phase-locked loop. The power supply filter and bypass schemes discussed in this section should be adequate to eliminate power supply noise-related problems in most designs.
Crystal Oscillator Input Interface
Figure 9 illustrates a parallel resonant crystal with its associated load capacitors. The capacitor values shown were determined using a 26.5625 MHz, 18 pF parallel resonant crystal and were chosen to minimize the ppm error. Capacitor values can be adjusted slightly for different board layouts to optimize accuracy.
3.3 V VCC 0.01 mF
10 W
VCCA 0.01 mF 10 mF
Figure 8. Power Supply Filtering
C1 33 pF X1 18 pF Parallel Crystal C2 27 pF
XOUT
The NB3N3011 features an integrated crystal oscillator to minimize system implementation costs. The oscillator circuit is a parallel resonant circuit and thus, for optimum performance, a parallel resonant crystal should be used. As the oscillator is somewhat sensitive to loading on its inputs, the user is advised to mount the crystal as close to the NB3N3011 as possible to avoid any board level parasitics. Surface mount crystals are recommended, but not required.
XIN
Figure 9. Crystal Input Interface
APPLICATION SCHEMATIC Figure 10 shows a schematic example of the NB3N3011. An example of LVPECL termination is shown in this schematic. Additional LVPECL termination approaches are shown in the AND8020 Application Note. In this example, an 18 pF parallel resonant 26.5625MHz crystal is used for generating 106.25 MHz output frequency. The C1 = 27 pF and C2 = 33 pF are recommended for frequency accuracy. For different board layout, the C1 and C2 values may be slightly adjusted for optimizing frequency accuracy.
VCC VCC R2 10 C3 10 mF VCCA C4 0.01 mF 1 U1 VCCA 2V EE 3X OUT 4 XIN 8 VCC 7 Q Q6 NC 5 Q VCC R3 ZO = 50 W 133 R5 133
+ Q ZO = 50 W R4 82.5 - R6 82.5
C2 33 pF
18 pF
X1
C1 27 pF
VCC = 3.3 V
C5 0.1 m
Figure 10. Typical Application Schematic http://onsemi.com
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NB3N3011
PC Board Layout Example
Figure 11 shows a representative board layout for the NB3N3011. There exists many different potential board layouts and the one pictured is but one. The crystal X1 footprint shown in this example allows installation of either surface mount HC49S or through-hole HC49 package. The footprints of other components in this example are listed in Table 9. There should be at least one decoupling capacitor per power pin. The decoupling capacitors should be located as close as possible to the power pins. The layout assumes that the board has clean analog power ground plane. The important aspect of the layout in Figure 11 is the low impedance connections between VCC and GND for the bypass capacitors. Combining good quality general purpose chip capacitors with good PCB layout techniques will produce effective capacitor resonances at frequencies adequate to supply the instantaneous switching current for the NB3N3011 outputs. It is imperative that low inductance chip capacitors are used. It is equally important that the board layout not introduce any of the inductance saved by using the leadless capacitors. Thin interconnect traces between the capacitor and the power plane should be avoided and multiple large vias should be used to tie the capacitors to the buried power planes. Fat interconnect and large vias will help to minimize layout induced inductance and thus maximize the series resonant point of the bypass capacitors. The voltage amplitude across the crystal is relatively small. It is imperative that no actively switching signals cross under the crystal as crosstalk energy coupled to these lines could significantly impact the jitter of the device.
Table 9. Footprint Table
Reference C1, C2 C3 C4, C5 R2 Size 0402 0805 0603 0603
C2
C1
Figure 11. PC Board Layout
Q Driver Device Q
Zo = 50 W
D Receiver Device
Zo = 50 W 50 W 50 W
D
VTT VTT = VCC - 2.0 V
Figure 12. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
ORDERING INFORMATION
Device NB3N3011DTG NB3N3011DTR2G Package TSSOP8 4.4 mm (Pb-Free) TSSOP8 4.4 mm (Pb-Free) Shipping 100 Units / Rail 2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NB3N3011
PACKAGE DIMENSIONS
TSSOP-8 CASE 948S-01 ISSUE B
8x
K REF 0.10 (0.004)
M
0.20 (0.008) T U
S
TU
S
V
S
2X
L
PIN 1 IDENT 1 4
B -U-
J J1
0.20 (0.008) T U
S
A -V- C
0.076 (0.003) D -T- SEATING
PLANE
G P N P1
DETAIL E
N
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
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ECC C EEEE CEEE CC EEEE CCC
K1 K 0.25 (0.010) M F DETAIL E
L/2
8
5
SECTION N-N -W-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 2.90 3.10 4.30 4.50 --- 1.10 0.05 0.15 0.50 0.70 0.65 BSC 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ --- 2.20 --- 3.20 INCHES MIN MAX 0.114 0.122 0.169 0.177 --- 0.043 0.002 0.006 0.020 0.028 0.026 BSC 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ --- 0.087 --- 0.126
DIM A B C D F G J J1 K K1 L M P P1
NB3N3011/D

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